1. Field
The disclosed technology relates to an organic light emitting display and a method of driving the same, and more particularly, to an organic light emitting display capable of displaying an image with uniform brightness and a method of driving the same.
2. Description of the Related Technology
Recently, various flat panel displays (FPDs) having reduced weight and volume as compared to cathode ray tubes (CRTs) have been developed. The FPDs include liquid crystal displays (LCDs), field emission displays (FEDs), plasma display panels (PDPs), and organic light emitting diode (OLED) displays.
Among the FPDs, the organic light emitting diode displays display images using OLEDs that generate light through the re-combination of electrons and holes. The organic light emitting diode displays have high response speed and are driven with low power consumption.
An organic light emitting diode display includes a plurality of data lines, scan lines, and pixels arranged at intersections of the scan and data lines. In most embodiments, each pixel includes an organic light emitting diode, at least two transistors including a drive transistor, and at least one capacitor.
A three dimensional (3D) organic light emitting diode display divides one frame period (e.g. about 16.6 ms) into two fields in order to realize a three dimensional (3D) image. In one frame period, a left image is displayed in a first field and a right image is displayed in a second field.
Shutter glasses receive light from a left lens in the first field and receive light from a right lens in the second frame. A viewer wearing the shutter glasses recognizes the image supplied through the shutter glasses in 3D. However, in a conventional art, due to a time difference between the first field and the second field, a uniform image may not be displayed.
In further detail, because a horizontal synchronizing signal Hsync and a vertical synchronizing signal Vsync are input from a system to a panel, additional hardware or circuitry for adjusting timing is to be included in the panel to manage the synchronizing signals. Accordingly, manufacturing cost increases. Therefore, a method in which a data enable (hereinafter, referred to as DE) signal and data are input from the system to the panel so that the hardware is omitted and the panel generates the horizontal synchronizing signal Hsync and the vertical synchronizing signal Vsync while counting the DE signals is used.
The DE signals generated based on data of one line have the same input period as the horizontal synchronizing signal Hsync. Therefore, the horizontal synchronizing signal Hsync may be generated by counting the DE signals. In addition, the vertical synchronizing signal Hsync may be generated based on a number of DE count signals.
If the DE signals and the data are supplied by the system, as illustrated in FIG. 1, a time difference is generated between odd frames and even frames. For example, in the case of the panel having 1,080 valid lines, the 1,080 DE signals are input to the respective frames. Accordingly, 1,080 count signals are generated by the respective frames (ith and (i+1)th frames).
The timing controller additionally generates counting signals based on the periods of the DE signals in a blank period after 1,080. In this case, 1,200 counting signals are generated in an ith (i is an odd number or an even number) frame and 1,110 counting signals are generated in an (i+1)th frame. In this example, the ith frame has a duration of 16.8 ms and the (i+1)th frame has a duration of 16.4 ms.
In such a panel, when a frame is divided into two fields in order to display a 3D image, the first field and the second field included in the (i+1)th frame and the first field included in the ith frame has a duration of 8.2 ms and the second field included in the ith frame has a duration of 8.6 ms. Therefore, the second field emission time of the ith frame is set to be longer than the emission times of adjacent fields so that an image with non-uniform brightness (for example, a flicker phenomenon) is displayed.